View TUSB1046A-DCI_9055236.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. TUSB1046A-DCI sllsf13 ? june 2017 TUSB1046A-DCI usb type-c ? displayport ? alt mode 10-gbps linear redriver crosspoint switch 1 1 features 1 ? usb type-c crosspoint switch supporting ? usb 3.1 ssp + 2 displayport lanes ? 4 displayport lanes ? usb 3.1 gen 1/gen 2 up to 10 gbps ? displayport 1.4 up to 8.1 gbps (hbr3) ? vesa ? displayport alt mode dfp redriving crosspoint switch supporting c, d, e and f configurations ? ultra-low-power architecture ? linear redriver with up to 14 db equalization ? transparent to displayport link training ? automatic lfps de-emphasis control to meet usb 3.1 certification requirements ? configuration through gpio or i 2 c ? intel proprietary dci capability on usb type-c for closed chassis debugging ? hot-plug capable ? industrial temperature range: ? 40 o c to 85 o c (tusb1046ai-dci) ? commercial temperature range: 0 o c to 70 o c (tusb1046-dci) ? 4 mm x 6 mm, 0.4 mm pitch wqfn package 2 applications ? tablets ? notebooks ? desktops ? docking stations 3 description the TUSB1046A-DCI is a vesa usb type-c ? alt mode redriving switch supporting usb 3.1 data rates up to 10 gbps and displayport 1.4 up to 8.1 gbps for downstream facing port (host). the device is used for configurations c, d, e, and f from the vesa displayport alt mode on usb type-c standard version 1.1. this protocol-agnostic linear redriver is also capable of supporting other usb type-c alt mode interfaces. the TUSB1046A-DCI provides several levels of receive linear equalization to compensate for inter- symbol interference (isi) due to cable and board trace loss. the device operates on a single 3.3-v supply and comes in a commercial temperature range and industrial temperature range. device information (1) part number package body size (nom) TUSB1046A-DCI wqfn (40) 4.00 mm x 6.00 mm tusb1046ai-dci (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematics TUSB1046A-DCI eye diagram TUSB1046A-DCI usb host gpu TUSB1046A-DCI type-c receptacle pd controller d+/- sstx ssrx dp0 dp1 dp2 dp3 auxp auxn sbu1 sbu2 cc1 cc2 control hpd ctl flip 0 1 tx1 tx2 rx1 rx2 hpdin copyright ? 2017, texas instruments incorporated tools & software technical documents ordernow productfolder support &community
2 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 5 6.5 power supply characteristics ................................... 6 6.6 dc electrical characteristics .................................... 6 6.7 ac electrical characteristics ..................................... 7 6.8 dci specific electrical characteristics ...................... 8 6.9 timing requirements ................................................ 9 6.10 switching characteristics ........................................ 9 6.11 typical characteristics .......................................... 10 7 parameter measurement information ................ 12 8 detailed description ............................................ 14 8.1 overview ................................................................. 14 8.2 functional block diagram ....................................... 15 8.3 feature description ................................................. 16 8.4 device functional modes ........................................ 17 8.5 programming ........................................................... 22 8.6 register maps ......................................................... 24 9 application and implementation ........................ 29 9.1 application information ............................................ 29 9.2 typical application ................................................. 29 9.3 system examples .................................................. 33 10 power supply recommendations ..................... 38 11 layout ................................................................... 39 11.1 layout guidelines ................................................. 39 11.2 layout example .................................................... 39 12 device and documentation support ................. 40 12.1 related links ........................................................ 40 12.2 receiving notification of documentation updates 40 12.3 community resources .......................................... 40 12.4 trademarks ........................................................... 40 12.5 electrostatic discharge caution ............................ 40 12.6 glossary ................................................................ 40 13 mechanical, packaging, and orderable information ........................................................... 40 4 revision history date revisions notes june 2017 * initial release
3 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 5 pin configuration and functions rnq package 40-pin (wqfn) top view pin functions pin i/o description name no. dp0p 9 diff i dp differential positive input for displayport lane 0. dp0n 10 diff i dp differential negative input for displayport lane 0. dp1p 12 diff i dp differential positive input for displayport lane 1. dp1n 13 diff i dp differential negative input for displayport lane 1. dp2p 15 diff i dp differential positive input for displayport lane 2. dp2n 16 diff i dp differential negative input for displayport lane 2. dp3p 18 diff i dp differential positive input for displayport lane 3. dp3n 19 diff i dp differential negative input for displayport lane 3. rx1n 31 diff i/o differential negative output for displayport or differential negative input for usb3.1 downstream facing port. rx1p 30 diff i/o differential positive output for displayport or differential positive input for usb3.1 downstream facing port. tx1n 34 diff o differential negative output for displayport or usb3.1 downstream facing port. tx1p 33 diff o differential positive output for displayport or usb 3.1 downstream facing port. tx2p 37 diff o differential positive output for displayport or usb 3.1 downstream facing port. tx2n 36 diff o differential negative output for displayport or usb 3.1 downstream facing port. rx2p 40 diff i/o differential positive output for displayport or differential positive input for usb3.1 downstream facing port. rx2n 39 diff i/o differential negative output for displayport or differential negative input for usb3.1 downstream facing port. 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 12 11 10 9 8 7 vcc dpeq1 vcc sseq1 25 28 26 27 36 35 34 33 32 31 30 29 37 38 39 40 tx2p rx1p dp1p sstxp dp0p rx2p ssrxn dp2p dp2n tx2n dp1n dp0n ssrxp rx1n sstxn rx2n dp3p dp3n hpdin/dci_clk tx1p tx1n eq0 sbu2 sbu1 eq1 i2c_en cad_snk/dci_dat dpeq0/a1 ctl0/sda flip/scl vcc vcc ctl1/hpdin sseq0/a0 auxp auxn thermal pad gnd
4 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin i/o description name no. sstxp 8 diff i differential positive input for usb3.1 upstream facing port. sstxn 7 diff i differential negative input for usb3.1 upstream facing port. ssrxp 5 diff o differential positive output for usb3.1 upstream facing port. ssrxn 4 diff o differential negative output for usb3.1 upstream facing port. eq1 35 4 level i this pin along with eq0 sets the usb receiver equalizer gain for downstream facing rx1 and rx2 when usb used. eq0 38 4 level i this pin along with eq1 sets the usb receiver equalizer gain for downstream facing rx1 and rx2 when usb used. cad_snk/ dci_dat 29 i/o (pd) when i2c_en ! = 0, this pin functions as dci data output leave open if not used. when i2c_en = 0 , this pin is cad_snk (l = aux snoop enabled and h = aux snoop disabled with all lanes active). hpdin/ dci_clk 32 i/o (pd) when i2c_en ! = 0, this pin functions as dci clock output leave open if not used. when i2c_en = 0, this pin is an input for hot plug detect received from displayport sink. when hpdin is low for greater than 2ms, all displayport lanes are disabled while the aux to sbu switch will remain closed. i2c_en 17 4 level i i 2 c programming mode or gpio programming select. i2c is only disabled when this pin is ? 0". 0 = gpio mode (i 2 c disabled) r = ti test mode (i 2 c enabled at 3.3 v) f = i 2 c enabled at 1.8 v 1 = i 2 c enabled at 3.3 v. sbu1 27 i/o, cmos sbu1. this pin should be dc coupled to the sbu1 pin on the type-c receptacle. a 2-m ohm resistor to gnd is also recommended. sbu2 26 i/o, cmos sbu2. this pin should be dc coupled to the sbu2 pin on the type-c receptacle. a 2-m ohm resistor to gnd is also recommended. auxp 24 i/o, cmos auxp. displayport aux positive i/o connected to the displayport source through a ac coupling capacitor. in addition to ac coupling capacitor, this pin also requires a 100k resistor to gnd. this pin along with auxn is used by the TUSB1046A-DCI for aux snooping and is routed to sbu1/2 based on the orientation of the type-c. auxn 25 i/o, cmos auxn. displayport aux negative i/o connected to the displayport source through a ac coupling capacitor. in addition to ac coupling capacitor, this pin also requires a 100k resistor to dp_pwr (3.3v). this pin along with auxp is used by the TUSB1046A-DCI for aux snooping and is routed to sbu1/2 based on the orientation of the type-c. dpeq1 2 4 level i displayport receiver eq. this along with dpeq0 will select the displayport receiver equalization gain. dpeq0/a1 14 4 level i displayport receiver eq. this along with dpeq1 will select the displayport receiver equalization gain. when i2c_en is not ? 0 ? , this pin will also set the TUSB1046A-DCI i 2 c address. sseq1 3 4 level i along with sseq0, sets the usb receiver equalizer gain for upstream facing sstxp/n. sseq0/a0 11 4 level i along with sseq1, sets the usb receiver equalizer gain for upstream facing sstxp/n. when i2c_en is not ? 0 ? , this pin will also set the TUSB1046A-DCI i 2 c address. flip/scl 21 2 level i when i2c_en= ? 0 ? this is flip control pin, otherwise this pin is i 2 c clock. . when used for i 2 c clock pullup to i 2 c master's vcc i2c supply. ctl0/sda 22 2 level i when i2c_en= ? 0 ? this is a usb3.1 switch control pin, otherwise this pin is i 2 c data. when used for i 2 c data pullup to i 2 c master's vcc i2c supply. ctl1/hpdin 23 2 level i (failsafe) (pd) dp alt mode switch control pin. when i2c_en = ? 0 ? , this pin will enable or disable displayport functionality. otherwise, when i2c_en is not "0", displayport functionality is enabled and disabled through i 2 c registers. l = displayport disabled. h = displayport enabled. when i2c_en is not "0" this pin is an input for hot plug detect received from displayport sink. when this hpdin is low for greater than 2 ms, all displayport lanes are disabled and aux to sbu switch will remain closed. vcc 1, 6, 20, 28 p 3.3-v power supply gnd thermal pad g ground
5 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to the gnd terminals. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage range (2) , v cc ? 0.3 4 v voltage range at any input or output pin differential voltage between positive and negative inputs 2.5 v voltage at differential inputs ? 0.5 v cc + 0.5 v cmos inputs ? 0.5 v cc + 0.5 v maximum junction temperature, t j 125 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 5000 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 1500 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v cc main power supply 3 3.3 3.6 v supply ramp requirement 100 ms v (12c) supply that external resistors are pulled up to on sda and scl 1.7 3.6 v v (psn) supply noise on v cc pins 100 mv t a operating free-air temperature TUSB1046A-DCI 0 70 c tusb1046ai-dci ? 40 85 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) TUSB1046A-DCI unit rnq (wqfn) 40 pins r ja junction-to-ambient thermal resistance 37.6 c/w r jc(top) junction-to-case (top) thermal resistance 20.7 c/w r jb junction-to-board thermal resistance 9.5 c/w jt junction-to-top characterization parameter 0.2 c/w jb junction-to-board characterization parameter 9.4 c/w r jc(bot) junction-to-case (bottom) thermal resistance 2.3 c/w
6 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 6.5 power supply characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit p cc(active-usb) average active power usb only link in u0 with gen2 data transmission. en, eq cntrl pins = nc, k28.5 pattern at 10 gbps, v id = 1000 mv pp ; ctl1 = l; ctl0 = h 335 mw p cc(active-usb-dp1) average active power usb + 2 lane dp link in u0 with gen2 data transmission. en, eq cntrl pins = nc, k28.5 pattern at 10 gbps, v id = 1000 mv pp ; ctl1 = h; ctl0 = h 634 mw p cc(active--dp) average active power 4 lane dp only four active dp lanes operating at 8.1gbps; ctl1 = h; ctl0 = l; 660 mw p cc(nc-usb) average power with no connection no gen1 device is connected to txp/txn; ctl1 = l; ctl0 = h; 2.4 mw p cc(u2u3) average power in u2/u3 link in u2 or u3 usb mode only; ctl1 = l; ctl0 = h; 3 mw p cc(shutdown) device shutdown ctl1 = l; ctl0 = l; i2c_en = 0; 0.85 mw 6.6 dc electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit 4-state cmos inputs(eq[1:0], sseq[1:0], dpeq[1:0], i2c_en) i ih high level input current v cc = 3.6 v; v in = 3.6 v 20 80 a i il low level input current v cc = 3.6 v; v in = 0 v ? 160 -40 a 4-level v th threshold 0 / r v cc = 3.3 v 0.55 v threshold r/ float v cc = 3.3 v 1.65 v threshold float / 1 v cc = 3.3 v 2.7 v r pu internal pull-up resistance 35 k r pd internal pull-down resistance 95 k 2-state cmos input (ctl0, ctl1, flip, cad_snk, hpdin) ctl1, ctl0 and flip are failsafe. v ih high-level input voltage 2 3.6 v v il low-level input voltage 0 0.8 v r pd internal pull-down resistance for ctl1 500 k ? r (enpd) internal pull-down resistance for cad_snk (pin 29), and hpdin (pin 32) 150 k ? i ih high-level input current v in = 3.6 v ? 25 25 a i il low-level input current v in = gnd, v cc = 3.6 v ? 25 25 a i 2 c control pins scl, sda v ih high-level input voltage i2c_en = 0 0.7 x v (i2c) 3.6 v v il low-level input voltage i2c_en = 0 0 0.3 x v (i2c) v v ol low-level output voltage i2c_en = 0; i ol = 3 ma 0 0.4 v i ol low-level output current i2c_en = 0; v ol = 0.4 v 20 ma i i(i2c) input current on sda pin 0.1 x v (i2c) < input voltage < 3.3 v ? 10 10 a c i(i2c) input capacitance 10 pf c (i2c_fm+_bus) i2c bus capacitance for fm+ (1mhz) 150 pf c (i2c_fm_bus) i2c bus capacitance for fm (400khz) 150 pf r (ext_i2c_fm+) external resistors on both sda and scl when operating at fm+ (1mhz) c (i2c_fm+_bus) = 150 pf 620 820 910 ? r (ext_i2c_fm) external resistors on both sda and scl when operating at fm (400khz) c (i2c_fm_bus) = 150 pf 620 1500 2200 ?
7 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 6.7 ac electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit usb gen 2 differential receiver (rx1p/n, rx2p/n, sstxp/n) v (rx-diff-pp) input differential peak-peak voltage swing linear dynamic range ac-coupled differential peak-to-peak signal measured post ctle through a reference channel 2000 mvpp v (rx-dc-cm) common-mode voltage bias in the receiver (dc) 0 v r (rx-diff-dc) differential input impedance (dc) present after a gen2 device is detected on txp/txn 72 120 r (rx-cm-dc) receiver dc common mode impedance present after a gen2 device is detected on txp/txn 18 30 z (rx-high-imp-dc-pos) common-mode input impedance with termination disabled (dc) present when no gen2 device is detected on txp/txn. measured over the range of 0-500mv with respect to gnd. 25 k v (signal-det-diff-pp) input differential peak-to-peak signal detect assert level at 10 gbps, no input loss, prbs7 pattern 80 mv v (rx-idle-det-diff-pp) input differential peak-to-peak signal detect de-assert level at 10 gbps, no input loss, prbs7 pattern 60 mv v (rx-lfps-det-diff-pp) low frequency periodic signaling (lfps) detect threshold below the minimum is squelched 100 300 mv v (rx-cm-ac-p) peak rx ac common-mode voltage measured at package pin 150 mv c (rx) rx input capacitance to gnd at 5 ghz 0.5 1 pf r l(rx-diff) differential return loss 50 mhz ? 1.25 ghz at 90 ? 19 db 5 ghz at 90 ? 10 db r l(rx-cm) common-mode return loss 50 mhz ? 5 ghz at 90 ? 10 db e q(ss_tx) receiver equalization for upstream facing port sseq[1:0] at 5 ghz 11 db e q(ss_rx) receiver equalization for downstream facing ports eq[1:0] at 5 ghz 9 db usb gen 2 differential transmitter (tx1p/n, tx2p/n, ssrxp/n) v tx(diff-pp) transmitter dynamic differential voltage swing range. 1600 mv pp v tx(rcv-detect) amount of voltage change allowed during receiver detection 600 mv v tx(cm-idle-delta) transmitter idle common-mode voltage change while in u2/u3 and not actively transmitting lfps ? 600 600 mv v tx(dc-cm) common-mode voltage bias in the transmitter (dc) 1.75 v v tx(cm-ac-pp-active) tx ac common-mode voltage active max mismatch from txp + txn for both time and amplitude 100 mv pp v tx(idle-diff-ac-pp) ac electrical idle differential peak-to- peak output voltage at package pins 0 10 mv v tx(idle-diff-dc) dc electrical idle differential output voltage at package pins after low pass filter to remove ac component 0 14 mv v tx(cm-dc-active-idle- delta) absolute dc common-mode voltage between u1 and u0 at package pin 200 mv r tx(diff) differential impedance of the driver 75 120 c ac(coupling) ac coupling capacitor 75 265 nf r tx(cm) common-mode impedance of the driver measured with respect to ac ground over 0 ? 500 mv 18 30 i tx(short) tx short circuit current tx shorted to gnd 67 ma c tx(parasitic) tx input capacitance for return loss at package pins, at 5 ghz 1.25 pf r ltx(diff) differential return loss 50 mhz ? 1.25 ghz at 90 -15 db 5 ghz at 90 -13 db r ltx(cm) common-mode return loss 50 mhz ? 5 ghz at 90 -13 db ac characteristics crosstalk differential crosstalk between tx and rx signal pairs at 5 ghz ? 30 db c (p1db-lf) low frequency 1-db compression point at 100 mhz, 200 mv pp < v id < 2000 mv pp 1300 mv pp
8 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated ac electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit c (p1db-hf) high frequency 1-db compression point at 5 ghz, 200 mv pp < v id < 2000 mv pp 1000 mv pp f lf low frequency cutoff 200 mv pp < v id < 2000 mv pp 20 50 khz tx output deterministic jitter 200 mv pp < v id < 2000 mv pp , prbs7, 10 gbps 0.11 uipp 200 mv pp < v id < 2000 mv pp , prbs7, 8.1 gbps 0.08 uipp tx output total jitter 200 mv pp < v id < 2000 mv pp , prbs7, 10 gbps 0.15 uipp 200 mv pp < v id < 2000 mv pp , prbs7, 8.1 gbps 0.135 uipp displayport receiver (dp[3:0]p or dp[3:0]n) v id(pp) peak-to-peak input differential dynamic voltage range 2000 v v ic input common mode voltage 0 v c (ac) ac coupling capacitance 75 200 nf e q(dp) receiver equalization dpeq[1:0] at 4.05 ghz 14 db d r data rate hbr3 8.1 gbps r (ti) input termination resistance 80 100 120 displayport transmitter (tx1p or tx1n, tx2p or tx2n, rx1p or rx1n, rx2p or rx2n) i tx(short) tx short circuit current tx shorted to gnd 67 ma v tx(dc-cm) common-mode voltage bias in the transmitter (dc) 1.75 v auxp or auxn and sbu1 or sbu2 r on output on resistance v cc = 3.3v; v i = 0 to 0.4 v for auxp; v i = 2.7 v to 3.6 v for auxn 5 10 r on on resistance mismatch within pair v cc = 3.3 v; v i = 0 to 0.4 v for auxp; v i = 2.7 v to 3.6 v for auxn 2.5 r on(flat) on resistance flatness (ron max ? ron min) measured at identical vcc and temperature v cc = 3.3 v; v i = 0 to 0.4 v for auxp; v i = 2.7 v to 3.6 v for auxn 2 v (auxp_dc_cm) aux channel dc common mode voltage for auxp and sbu1. v cc = 3.3 v 0 0.4 v v (auxn_dc_cm) aux channel dc common mode voltage for auxn and sbu2 v cc = 3.3 v 2.7 3.6 v c (aux_on) on-state capacitance v cc = 3.3 v; ctl1 = 1; v i = 0 v or 3.3 v 4 7 pf c (aux_off) off-state capacitance v cc = 3.3 v; ctl1 = 0; v i = 0 v or 3.3 v 3 6 pf 6.8 dci specific electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit dci_clk and dci_dat lvcmos outputs v ol low-level output voltage v cc = 3 v; i ol = 2 ma; c l = 10 pf 0.45 v v oh high-level output voltage v cc = 3 v; i ol = ? 2 ma; 2.4 v r dci output characteristic impedance 21 25 33 t period dci clock period measured at 50% 6.67 ns t valid rising edge of dci clock to dci data valid 1 ns t dci_rise dci output rise time measured at 20% to 80%. 350 ps t dci_fall dci output fall time measured at 80% to 20% 350 ps
9 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 6.9 timing requirements min nom max unit usb gen 1 t idleentry delay from u0 to electrical idle see figure 14 10 ns t idelexit_u1 u1 exist time: break in electrical idle to the transmission of lfps see figure 14 6 ns t idleexit_u2u3 u2/u3 exit time: break in electrical idle to transmission of lfps 10 s t rxdet_intvl rx detect interval while in disconnect 12 ms t idleexit_disc disconnect exit time 10 s t exit_shtdn shutdown exit time 1 ms t diff_dly differential propagation delay see figure 13 300 ps t r, t f output rise/fall time (see figure 15 ) 20%-80% of differential voltage measured 1.7 inch from the output pin 35 ps t rf_mm output rise/fall time mismatch 20%-80% of differential voltage measured 1.7 inch from the output pin 2.6 ps 6.10 switching characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit auxp or auxn and sbu1 or sbu2 t aux_pd switch propagation delay 400 ps t aux_sw_off switching time ctl1 to switch off. not including tctl1_debounce. 500 ns t aux_sw_on switching time ctl1 to switch on 500 ns t aux_intra intra-pair output skew 100 ps usb3.1 and displayport mode transition requirement gpio mode t gp_usb_4dp min overlap of ctl0 and ctl1 when transitioning from usb 3.1 only mode to 4-lane displayport mode or vice versa. 4 s ctl1 and hpdin t ctl1_debounce ctl1 and hpdin debounce time when transitioning from h to l. 2 10 ms i 2 c (refer to figure 11 ) f scl i 2 c clock frequency 1 mhz t buf bus free time between start and stop conditions 0.5 s t hdsta hold time after repeated start condition. after this period, the first clock pulse is generated 0.26 s t low low period of the i 2 c clock 0.5 s t high high period of the i 2 c clock 0.26 s t susta setup time for a repeated start condition 0.26 s t hddat data hold time 0 s t sudat data setup time 50 ns t r rise time of both sda and scl signals 120 ns t f fall time of both sda and scl signals 20 (v (i2c) /5.5 v) 120 ns t susto setup time for stop condition 0.26 s c b capacitive load for each bus line 150 pf
10 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 6.11 typical characteristics figure 1. displayport eq settings curves figure 2. usb rx eq settings curves figure 3. usb tx eq settings curves figure 4. displayport linearity curves at 4.05 ghz figure 5. usb tx linearity curves at 5 ghz figure 6. usb rx linearity curves at 5 ghz frequency (ghz) sdd21 (db) -15 -10 -5 0 5 10 15 0.01 0.1 1 10 d001 eq0 eq1 eq2 eq3 eq4 eq5 eq6 eq7 eq8 eq9 eq10 eq11 eq12 eq13 eq14 eq15 frequency (ghz) sdd21 (db) -15 -10 -5 0 5 10 15 0.01 0.1 1 10 d002 eq0 eq1 eq2 eq3 eq4 eq5 eq6 eq7 eq8 eq9 eq10 eq11 eq12 eq13 eq14 eq15 frequency (ghz) sdd21 (db) -15 -10 -5 0 5 10 15 0.01 0.1 1 10 d003 eq0 eq1 eq2 eq3 eq4 eq5 eq6 eq7 eq8 eq9 eq10 eq11 eq12 eq13 eq14 eq15 differential input voltage (v) differential output voltage (v) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 d004 eq0 eq1 eq2 eq3 eq4 eq5 eq6 eq7 eq8 eq9 eq10 eq11 eq12 eq13 eq14 eq15 differential input voltage (v) differential output voltage (v) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 d006 eq0 eq1 eq2 eq3 eq4 eq5 eq6 eq7 eq8 eq9 eq10 eq11 eq12 eq13 eq14 eq15 differential input voltage (v) differential output voltage (v) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 d005 eq0 eq1 eq2 eq3 eq4 eq5 eq6 eq7 eq8 eq9 eq10 eq11 eq12 eq13 eq14 eq15
11 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) figure 7. input return loss performance figure 8. output return loss performance figure 9. displayport hbr3 eye-pattern performance with 12-inch input pcb trace at 8.1 gbps figure 10. usb 3.1 gen2 eye-pattern performance with 12-inch input pcb trace at 10 gbps time (20.57 ps/div) output voltage (75 mv/div) time (16.67 ps/div) output voltage ( 150 mv / div ) frequency (ghz) sdd22 (db) -30 -25 -20 -15 -10 -5 0 5 0.01 0.1 1 10 d008 rx1 rx2 tx1 tx2 ssrx frequency (ghz) sdd11 (db) -40 -35 -30 -25 -20 -15 -10 -5 0 5 0.01 0.1 1 10 d007 dp0 dp1 dp2 dp3 sstx rx1 rx2
12 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 7 parameter measurement information figure 11. i 2 c timing diagram definitions figure 12. usb3.1 to 4-lane displayport in gpio mode figure 13. propagation delay t buf t hdsta t r t low t hddat t high t f t sudat t susta t hdsta t susto p s s p sda scl 30% 70% 30% 70% ctl0 pin ctl1 pin 4us (min) in out t diff_dly t diff_dly
13 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated parameter measurement information (continued) figure 14. electrical idle mode exit and entry delay figure 15. output rise and fall times figure 16. aux and sbu switch on and off timing diagram figure 17. dci clock propagation delay ctl1 v out 50% 90% 50% 10% t aux_sw_on t aux_sw_off + t ctl1_debounce rx1n or rx2n dci_clk v ih_min v ih_max t dci_clk_pd v oh_min v ol_max t dci_clk_pd t idleexit t idleentry in+ in- vcm out+ out- vcm v rx-lfps-det-diff-pp t r t f 20% 80%
14 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 8 detailed description 8.1 overview the TUSB1046A-DCI is a vesa usb type-c alt mode redriving switch supporting data rates up to 8.1 gbps for downstream facing port. these devices utilize 5 th generation usb redriver technology. the devices are utilized for dfp configurations c, d, e, and f from the vesa displayport alt mode on usb type-c. the TUSB1046A-DCI provides several levels of receive equalization to compensate for cable and board trace loss due to inter-symbol interference (isi) when usb 3.1 gen1/gen2 or displayport 1.4 signals travel across a pcb or cable. this device requires a 3.3-v power supply. it comes in a commercial temperature range and industrial temperature range. for a host application the TUSB1046A-DCI enables the system to pass both transmitter compliance and receiver jitter tolerance tests for usb 3.1 gen1/gen2 and displayport version 1.4 hbr3. the re-driver recovers incoming data by applying equalization that compensates for channel loss, and drives out signals with a high differential voltage. each channel has a receiver equalizer with selectable gain settings. the equalization should be set based on the amount of insertion loss before the TUSB1046A-DCI receivers. independent equalization control for each channel can be set using eq[1:0], sseq[1:0], and dpeq[1:0] pins. the TUSB1046A-DCI advanced state machine makes it transparent to hosts and devices. after power up, the TUSB1046A-DCI. periodically performs receiver detection on the tx pairs. if it detects a usb 3.1 gen1/gen2 receiver, the rx termination is enabled, and the TUSB1046A-DCI is ready to re-drive. the device ultra-low-power architecture operates at a 3.3-v power supply and achieves enhanced performance. the automatic lfps de-emphasis control further enables the system to be usb3.1 compliant.
15 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2 functional block diagram dp0p dp0n dp3p dp3n i2c_en dpeq[1:0]/a1 sseq[1:0]/a0 sbu2 sbu1 ctl0/sda flip/scl vcc auxp auxn sstxp ssrxn ssrxp sstxn tx2p rx1p rx2p tx2n rx1n rx2n cad_snk/dci_dat tx1p tx1n eq[1:0] hpdin/dci_clk driver eq eq eq eq eq driver driver driver driver eq eq term term detect term term term term term term term detect term detect term term m u x vreg mux mux fsm, control logic and registers dpeq_sel sseq_sel dpeq_sel dpeq_sel dpeq_sel sseq_sel eq_sel eq_sel eq_sel dp1p dp1n dp2p dp2n ctl1/hpdin aux rx i2c slave copyright ? 2017, texas instruments incorporated
16 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3 feature description 8.3.1 usb 3.1 the TUSB1046A-DCI supports usb 3.1 gen1/gen2 datarates up to 10 gbps. the TUSB1046A-DCI supports all the usb defined power states (u0, u1, u2, and u3). because the TUSB1046A-DCI is a linear redriver, it can ? t decode usb3.1 physical layer traffic. the TUSB1046A-DCI monitors the actual physical layer conditions like receiver termination, electrical idle, lfps, and superspeed signaling rate to determine the usb power state of the usb 3.1 interface. the TUSB1046A-DCI features an intelligent low frequency periodic signaling (lfps) detector. the lfps detector automatically senses the low frequency signals and disables receiver equalization functionality. when not receiving lfps, the TUSB1046A-DCI will enable receiver equalization based on the eq[1:0] and sseq[1:0] pins or values programmed into eq1_sel, eq2_sel, and sseq_sel registers. 8.3.2 displayport the TUSB1046A-DCI supports up to 4 displayport lanes at datarates up to 8.1gbps (hbr3). the tusb1046a- dci, when configured in displayport mode, monitors the native aux traffic as it traverses between displayport source and displayport sink. for the purposes of reducing power, the TUSB1046A-DCI manages the number of active displayport lanes based on the content of the aux transactions. the TUSB1046A-DCI snoops native aux writes to displayport sink ? s dpcd registers 0x00101 (lane_count_set) and 0x00600 (set_power_state). TUSB1046A-DCI disables/enables lanes based on value written to lane_count_set. the TUSB1046A-DCI disables all lanes when set_power_state is in the d3. otherwise active lanes will be based on value of lane_count_set. displayport aux snooping is enabled by default but can be disabled by changing the aux_snoop_disable register. once aux snoop is disabled, management of TUSB1046A-DCI displayport lanes are controlled through various configuration registers. when TUSB1046A-DCI is enabled for gpio mode (i2c_en = "0"), the cad_snk pin can be used to disable aux snooping. when cad_snk pin is high, the aux snooping functionality is disabled and all four displayport lanes will be active. 8.3.3 4-level inputs the TUSB1046A-DCI has (i2c_en, eq[1:0], dpeq[1:0], and sseq[1:0]) 4-level inputs pins that are used to control the equalization gain and place TUSB1046A-DCI into different modes of operation. these 4-level inputs utilize a resistor divider to help set the 4 valid levels and provide a wider range of control settings. there is an internal 30 k ? pull-up and a 94 k ? pull-down. these resistors, together with the external resistor connection combine to achieve the desired voltage level. table 1. 4-level control pin settings level settings 0 option 1: tie 1 k ? 5% to gnd. option 2: tie directly to gnd. r tie 20 k ? 5% to gnd. f float (leave pin open) 1 option 1: tie 1 k ? 5%to v cc . option 2: tie directly to v cc .
17 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated note all four-level inputs are latched on rising edge of internal reset. after t cfg_hd , the internal pull-up and pull-down resistors will be isolated in order to save power. 8.3.4 receiver linear equalization the purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in the system before the input of the TUSB1046A-DCI. the receiver overcomes these losses by attenuating the low frequency components of the signals with respect to the high frequency components. the proper gain setting should be selected to match the channel insertion loss before the input of the TUSB1046A-DCI receivers. two 4- level inputs pins enable up to 16 possible equalization settings. usb3.1 upstream path, usb3.1 downstream path, and displayport each have their own two 4-level inputs. the TUSB1046A-DCI also provides the flexibility of adjusting settings through i 2 c registers. 8.4 device functional modes 8.4.1 device configuration in gpio mode the TUSB1046A-DCI is in gpio configuration when i2c_en = ? 0 ? . the TUSB1046A-DCI supports the following configurations: usb 3.1 only, 2 displayport lanes + usb 3.1, or 4 displayport lanes (no usb 3.1). the ctl1 pin controls whether displayport is enabled. the combination of ctl1 and ctl0 selects between usb 3.1 only, 2 lanes of displayport, or 4-lanes of displayport as detailed in table 2 . the auxp or auxn to sbu1 or sbu2 mapping is controlled based on table 3 . after power-up (v cc from 0 v to 3.3 v), the TUSB1046A-DCI defaults to usb3.1 mode. the usb pd controller upon detecting no device attached to type-c port or usb3.1 operation not required by attached device must take TUSB1046A-DCI out of usb3.1 mode by transitioning the ctl0 pin from l to h and back to l. table 2. gpio configuration control ctl1 pin ctl0 pin flip pin TUSB1046A-DCI configuration vesa displayport alt mode dfp_d configuration l l l power down ? l l h power down ? l h l one port usb 3.1 - no flip ? l h h one port usb 3.1 ? with flip ? h l l 4 lane dp - no flip c and e h l h 4 lane dp ? with flip c and e h h l one port usb 3.1 + 2 lane dp- no flip d and f h h h one port usb 3.1 + 2 lane dp ? with flip d and f table 3. gpio auxp or auxn to sbu1 or sbu2 mapping ctl1 pin flip pin mapping h l auxp sbu1 auxn sbu2 h h auxp sbu2 auxn sbu1 l > 2 ms x open table 4 details the TUSB1046A-DCI ? s mux routing. this table is valid for both i 2 c and gpio configuration modes.
18 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated table 4. input to output mapping ctl1 pin ctl0 pin flip pin from to input pin output pin l l l na na l l h na na l h l rx1p ssrxp rx1n ssrxn sstxp tx1p sstxn tx1n l h h rx2p ssrxp rx2n ssrxn sstxp tx2p sstxn tx2p h l l dp0p rx2p dp0n rx2n dp1p tx2p dp1n tx2n dp2p tx1p dp2n tx1n dp3p rx1p dp3n rx1n h l h dp0p rx1p dp0n rx1n dp1p tx1p dp1n tx1n dp2p tx2p dp2n tx2n dp3p rx2p dp3n rx2n h h l rx1p ssrxp rx1n ssrxn sstxp tx1p sstxn tx1n dp0p rx2p dp0n rx2n dp1p tx2p dp1n tx2n h h h rx2p ssrxp rx2n ssrxn sstxp tx2p sstxn tx2n dp0p rx1p dp0n rx1n dp1p tx1p dp1n tx1n
19 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4.2 device configuration in i 2 c mode the TUSB1046A-DCI is in i 2 c mode when i2c_en is not equal to ? 0 ? . the same configurations defined in gpio mode are also available in i 2 c mode. the TUSB1046A-DCI usb3.1 and displayport configuration is controlled based on table 5 . the auxp or auxn to sbu1 or sbu2 mapping control is based on table 6 . table 5. i 2 c configuration control registers TUSB1046A-DCI configuration vesa displayport alt mode dfp_d configuration ctlsel1 ctlsel0 flipsel 0 0 0 power down ? 0 0 1 power down ? 0 1 0 one port usb 3.1 - no flip ? 0 1 1 one port usb 3.1 ? with flip ? 1 0 0 4 lane dp - no flip c and e 1 0 1 4 lane dp ? with flip c and e 1 1 0 one port usb 3.1 + 2 lane dp- no flip d and f 1 1 1 one port usb 3.1 + 2 lane dp ? with flip d and f table 6. i 2 c auxp or auxn to sbu1 or sbu2 mapping registers mapping aux_sbu_ovr 1 aux_sbu_ovr0 ctlsel1 flipsel 0 0 1 0 auxp sbu1 auxn sbu2 0 0 1 1 auxp sbu2 auxn sbu1 0 0 0 x open 0 1 x x auxp sbu1 auxn sbu2 1 0 x x auxp sbu2 auxn sbu1 1 1 x x open 8.4.3 displayport mode the TUSB1046A-DCI supports up to four displayport lanes at datarates up to 8.1 gbps. TUSB1046A-DCI can be enabled for displayport through gpio control or through i 2 c register control. when i2c_en is ? 0 ? , displayport is controlled based on table 2 . when not in gpio mode, enable of displayport functionality is controlled through i 2 c registers.
20 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4.4 linear eq configuration each of the TUSB1046A-DCI receiver lanes has individual controls for receiver equalization. the receiver equalization gain value can be controlled either through i 2 c registers or through gpios. table 7 details the gain value for each available combination when TUSB1046A-DCI is in gpio mode. these same options are also available in i 2 c mode by updating registers dp0eq_sel, dp1eq_sel, dp2eq_sel, dp3eq_sel, eq1_sel, eq2_sel, and sseq_sel. table 7. TUSB1046A-DCI receiver equalization gpio control equalization setting # usb3.1 downstream facing ports usb 3.1 upstream facing port all displayport lanes eq1 pin level eq0 pin level eq gain at 5 ghz (db) sseq1 pin level sseq0 pin level eq gain at 5 ghz (db) dpeq1 pin level dpeq0 pin level eq gain at 4.05 ghz (db) 0 0 0 -3.9 0 0 -1.8 0 0 1.0 1 0 r -1.7 0 r 0.2 0 r 3.3 2 0 f -0.1 0 f 1.7 0 f 4.9 3 0 1 1.4 0 1 3.2 0 1 6.5 4 r 0 2.4 r 0 4.2 r 0 7.5 5 r r 3.5 r r 5.3 r r 8.6 6 r f 4.4 r f 6.1 r f 9.5 7 r 1 5.2 r 1 7.0 r 1 10.4 8 f 0 5.9 f 0 7.7 f 0 11.1 9 f r 6.6 f r 8.3 f r 11.7 10 f f 7.1 f f 8.8 f f 12.3 11 f 1 7.6 f 1 9.3 f 1 12.8 12 1 0 8.0 1 0 9.7 1 0 13.2 13 1 r 8.5 1 r 10.1 1 r 13.6 14 1 f 8.8 1 f 10.4 1 f 14.0 15 1 1 9.2 1 1 10.8 1 1 14.4 8.4.5 usb3.1 modes the TUSB1046A-DCI monitors the physical layer conditions like receiver termination, electrical idle, lfps, and superspeed signaling rate to determine the state of the usb3.1 interface. depending on the state of the usb 3.1 interface, the TUSB1046A-DCI can be in one of four primary modes of operation when usb 3.1 is enabled (ctl0 = h or ctlsel0 = 1b1): disconnect, u2/u3, u1, and u0. the disconnect mode is the state in which TUSB1046A-DCI has not detected far-end termination on both upstream facing port (ufp) or downstream facing port (dfp). the disconnect mode is the lowest power mode of each of the four modes. the TUSB1046A-DCI remains in this mode until far-end receiver termination has been detected on both ufp and dfp. the TUSB1046A-DCI immediately exits this mode and enter u0 once far-end termination is detected. once in u0 mode, the TUSB1046A-DCI will redrive all traffic received on ufp and dfp. u0 is the highest power mode of all usb3.1 modes. the TUSB1046A-DCI remains in u0 mode until electrical idle occurs on both ufp and dfp. upon detecting electrical idle, the TUSB1046A-DCI immediately transitions to u1. the u1 mode is the intermediate mode between u0 mode and u2/u3 mode. in u1 mode, the TUSB1046A-DCI ufp and dfp receiver termination remains enabled. the ufp and dfp transmitter dc common mode is maintained. the power consumption in u1 is similar to power consumption of u0. next to the disconnect mode, the u2/u3 mode is next lowest power state. while in this mode, the tusb1046a- dci periodically performs far-end receiver detection. anytime the far-end receiver termination is not detected on either ufp or dfp, the TUSB1046A-DCI leaves the u2/u3 mode and transitions to the disconnect mode. it also monitors for a valid lfps. upon detection of a valid lfps, the TUSB1046A-DCI immediately transitions to the u0 mode. in u2/u3 mode, the TUSB1046A-DCI receiver terminations remain enabled but the tx dc common mode voltage is not maintained.
21 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated (1) following pins comprise cfg pins: i2c_en, eq[1:0], sseq[1:0], and dpeq[1:0]. (2) recommend cfg pins are stable when v cc is at min. 8.4.6 operation timing ? power up figure 18. power-up timing table 8. power-up timing (1) (2) parameter min max unit t d_pg v cc (minimum) to internal power good asserted high 500 s t cfg_su cfg(1) pins setup(2) 250 s t cfg_hd cfg(1) pins hold 10 s t ctl_db ctl[1:0] and flip pin debounce 16 ms t vcc_ramp vcc supply ramp requirement 100 ms t d_pg v cc internal power good t cfg_su t cfg_hd disabled usb3.1- only flip = 0 if (( ctl[1:0 ] == 2'b 00 | ctl[1:0 ] == 2'b 01 ) & flip == 0 ) { usb3.1- only no flip; } elseif ((ctl[1:0 ] == 2'b 00 | ctl[1:0 ] == 2'b01 ) & flip == 1 ) { usb3.1- only with flip ; } elseif (ctl[1:0 ] == 2'b 10 & flip == 0 ) { 4-lane dp no flip; } elseif (ctl[1:0 ] == 2'b 10 & flip == 1 ) { 4-lane dp with flip; } elseif (ctl[1:0 ] == 2'b 11 & flip == 0 ) { 2-lane dp usb3.1 no flip; } else { 2-lane dp usb3.1 with flip ; }; ctl[1:0 ] pins flip pin cfg pins in gpio mode disabled usb3.1- only flip = 0 TUSB1046A-DCI in i2c mode mode of operation determined by value of flipsel bit and ctlsel[1:0] bits at offset0x0a. default is usb3.1- only no flip. t ctl_db v cc (min) TUSB1046A-DCI
22 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5 programming for further programmability, the TUSB1046A-DCI can be controlled using i 2 c. the scl and sda pins are used for i 2 c clock and i 2 c data respectively. table 9. TUSB1046A-DCI i 2 c target address dpeq0/a1 pin level sseq0/a0 pin level bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (w/r) 0 0 1 0 0 0 1 0 0 0/1 0 r 1 0 0 0 1 0 1 0/1 0 f 1 0 0 0 1 1 0 0/1 0 1 1 0 0 0 1 1 1 0/1 r 0 0 1 0 0 0 0 0 0/1 r r 0 1 0 0 0 0 1 0/1 r f 0 1 0 0 0 1 0 0/1 r 1 0 1 0 0 0 1 1 0/1 f 0 0 0 1 0 0 0 0 0/1 f r 0 0 1 0 0 0 1 0/1 f f 0 0 1 0 0 1 0 0/1 f 1 0 0 1 0 0 1 1 0/1 1 0 0 0 0 1 1 0 0 0/1 1 r 0 0 0 1 1 0 1 0/1 1 f 0 0 0 1 1 1 0 0/1 1 1 0 0 0 1 1 1 1 0/1 the following procedure should be followed to write to TUSB1046A-DCI i 2 c registers: 1. the master initiates a write operation by generating a start condition (s), followed by the TUSB1046A-DCI 7- bit address and a zero-value ? w/r ? bit to indicate a write cycle. 2. the TUSB1046A-DCI acknowledges the address cycle. 3. the master presents the sub-address (i 2 c register within TUSB1046A-DCI) to be written, consisting of one byte of data, msb-first. 4. the TUSB1046A-DCI acknowledges the sub-address cycle. 5. the master presents the first byte of data to be written to the i 2 c register. 6. the TUSB1046A-DCI acknowledges the byte transfer. 7. the master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TUSB1046A-DCI. 8. the master terminates the write operation by generating a stop condition (p). the following procedure should be followed to read the TUSB1046A-DCI i 2 c registers: 1. the master initiates a read operation by generating a start condition (s), followed by the TUSB1046A-DCI 7- bit address and a one-value ? w/r ? bit to indicate a read cycle. 2. the TUSB1046A-DCI acknowledges the address cycle. 3. the TUSB1046A-DCI transmit the contents of the memory registers msb-first starting at register 00h or last read sub-address+1. if a write to the t i 2 c register occurred prior to the read, then the TUSB1046A-DCI shall start at the sub-address specified in the write. 4. the TUSB1046A-DCI shall wait for either an acknowledge (ack) or a not-acknowledge (nack) from the master after each byte transfer; the i 2 c master acknowledges reception of each data byte transfer. 5. if an ack is received, the TUSB1046A-DCI transmits the next byte of data. 6. the master terminates the read operation by generating a stop condition (p). the following procedure should be followed for setting a starting sub-address for i 2 c reads: 1. the master initiates a write operation by generating a start condition (s), followed by the TUSB1046A-DCI 7- bit address and a zero-value ? w/r ? bit to indicate a write cycle. 2. the TUSB1046A-DCI acknowledges the address cycle. 3. the master presents the sub-address (i 2 c register within TUSB1046A-DCI) to be written, consisting of one byte of data, msb-first.
23 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 4. the TUSB1046A-DCI acknowledges the sub-address cycle. 5. the master terminates the write operation by generating a stop condition (p). note if no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the i 2 c master terminates the read operation. if a i 2 c address write occurred prior to the read, then the reads start at the sub-address specified by the address write. table 10. register legend access tag name meaning r read the field may be read by software w write the field may be written by software s set the field may be set by a write of one. writes of zeros to the field have no effect. c clear the field may be cleared by a write of one. write of zero to the field have no effect. u update hardware may autonomously update this field. na no access not accessible or not applicable
24 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6 register maps 8.6.1 general register (address = 0x0a) [reset = 00000001] figure 19. general registers 7 6 5 4 3 2 1 0 reserved swap_hpdin eq_overrid e hpdin_ovrri de flipsel ctlsel[1:0]. r r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 11. general registers bit field type reset description 7:6 reserved. r 00 reserved. 5 swap_hpdin r/w 0 0 ? hpdin is in default location (default) 1 ? hpdin location is swapped (pin 23 to pin 32, or pin 32 to pin23). 4 eq_override r/w 0 setting of this field will allow software to use eq settings from registers instead of value sample from pins. 0 ? eq settings based on sampled state of the eq pins (sseq[1:0], eq[1:0], and dpeq[1:0]). 1 ? eq settings based on programmed value of each of the eq registers 3 hpdin_ovrride r/w 0 0 ? hpd in based on state of hpd_in pin (default) 1 ? hpd_in high. 2 flipsel r/w 0 flipsel. refer to table 5 and table 6 for this field functionality. 1:0 ctlsel[1:0]. r/w 01 00 ? disabled. all rx and tx for usb3 and displayport are disabled. 01 ? usb3.1 only enabled. (default) 10 ? four displayport lanes enabled. 11 ? two displayport lanes and one usb3.1 8.6.2 displayport control/status registers (address = 0x10) [reset = 00000000] figure 20. displayport control/status registers (0x10) 7 6 5 4 3 2 1 0 dp1eq_sel dp0eq_sel r/w/u r/w/u legend: r/w = read/write; r = read only; -n = value after reset table 12. displayport control/status registers (0x10) bit field type reset description 7:4 dp1eq_sel r/w/u 0000 field selects between 0 to 14db of eq for dp lane 1. when eq_override = 1 ? b0, this field reflects the sampled state of dpeq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for dp lane 1 based on value written to this field. 3:0 dp0eq_sel r/w/u 0000 field selects between 0 to 14db of eq for dp lane 0. when eq_override = 1 ? b0, this field reflects the sampled state of dpeq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for dp lane 0 based on value written to this field.
25 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.3 displayport control/status registers (address = 0x11) [reset = 00000000] figure 21. displayport control/status registers (0x11) 7 6 5 4 3 2 1 0 dp3eq_sel dp2eq_sel r/w/u r/w/u legend: r/w = read/write; r = read only; -n = value after reset table 13. displayport control/status registers (0x11) bit field type reset description 7:4 dp3eq_sel r/w/u 0000 field selects between 0 to 14db of eq for dp lane 3. when eq_override = 1 ? b0, this field reflects the sampled state of dpeq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for dp lane 3 based on value written to this field. 3:0 dp2eq_sel r/w/u 0000 field selects between 0 to 14db of eq for dp lane 2. when eq_override = 1 ? b0, this field reflects the sampled state of dpeq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for dp lane 2 based on value written to this field. 8.6.4 displayport control/status registers (address = 0x12) [reset = 00000000] figure 22. displayport control/status registers (0x12) 7 6 5 4 3 2 1 0 reserved set_power_state lane_count_set r ru ru legend: r/w = read/write; r = read only; -n = value after reset table 14. displayport control/status registers (0x12) bit field type reset description 7 reserved r 0 reserved 6:5 set_power_state r/u 00 this field represents the snooped value of the aux write to dpcd address 0x00600. when aux_snoop_disable = 1 ? b0, the TUSB1046A-DCI will enable/disable dp lanes based on the snooped value. when aux_snoop_disable = 1 ? b1, then dp lane enable/disable are determined by state of dpx_disable registers, where x = 0, 1, 2, or 3. this field is reset to 2 ? b00 by hardware when ctlsel1 changes from a 1 ? b1 to a 1 ? b0. 4:0 lane_count_set r/u 00000 this field represents the snooped value of aux write to dpcd address 0x00101 register. when aux_snoop_disable = 1 ? b0, tusb1046-dci will enable dp lanes specified by the snoop value. unused dp lanes will be disabled to save power. when aux_snoop_disable = 1 ? b1, then dp lanes enable/disable are determined by dpx_disable registers, where x = 0, 1, 2, or 3. this field is reset to 0x0 by hardware when ctlsel1 changes from a 1 ? b1 to a 1 ? b0.
26 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.5 displayport control/status registers (address = 0x13) [reset = 00000000] figure 23. displayport control/status registers (0x13) 7 6 5 4 3 2 1 0 aux_snoop_ disable reserved aux_sbu_ovr dp3_disable dp2_disable dp1_disable dp0_disable r/w r r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 15. displayport control/status registers (0x13) bit field type reset description 7 aux_snoop_disable r/w 0 0 ? aux snoop enabled. (default) 1 ? aux snoop disabled. 6 reserved r 0 reserved 5:4 aux_sbu_ovr r/w 00 this field overrides the auxp or auxn to sbu1 or sbu2 connect and disconnect based on ctl1 and flip. changing this field to 1 ? b1 will allow traffic to pass through aux to sbu regardless of the state of ctlsel1 and flipsel register 00 ? aux to sbu connect/disconnect determined by ctlsel1 and flipsel (default) 01 ? auxp - > sbu1 and auxn - > sbu2 connection always enabled. 10 ? auxp - > sbu2 and auxn - > sbu1 connection always enabled. 11 = aux to sbu open. 3 dp3_disable r/w 0 when aux_snoop_disable = 1 ? b1, this field can be used to enable or disable dp lane 3. when aux_snoop_disable = 1 ? b0, changes to this field will have no effect on lane 3 functionality. 0 ? dp lane 3 enabled (default) 1 ? dp lane 3 disabled. 2 dp2_disable r/w 0 when aux_snoop_disable = 1 ? b1, this field can be used to enable or disable dp lane 2. when aux_snoop_disable = 1 ? b0, changes to this field will have no effect on lane 2 functionality. 0 ? dp lane 2 enabled (default) 1 ? dp lane 2 disabled. 1 dp1_disable r/w 0 when aux_snoop_disable = 1 ? b1, this field can be used to enable or disable dp lane 1. when aux_snoop_disable = 1 ? b0, changes to this field will have no effect on lane 1 functionality. 0 ? dp lane 1 enabled (default) 1 ? dp lane 1 disabled. 0 dp0_disable r/w 0 disable. when aux_snoop_disable = 1 ? b1, this field can be used to enable or disable dp lane 0. when aux_snoop_disable = 1 ? b0, changes to this field will have no effect on lane 0 functionality. 0 ? dp lane 0 enabled (default) 1 ? dp lane 0 disabled. 8.6.6 usb3.1 control/status registers (address = 0x20) [reset = 00000000] figure 24. usb3.1 control/status registers (0x20) 7 6 5 4 3 2 1 0 eq2_sel eq1_sel r/w/u r/w/u legend: r/w = read/write; r = read only; -n = value after reset
27 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated table 16. usb3.1 control/status registers (0x20) bit field type reset description 7:4 eq2_sel r/w/u 0000 field selects between 0 to 9 db of eq for usb3.1 rx2 receiver. when eq_override = 1 ? b0, this field reflects the sampled state of eq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for usb3.1 rx2 receiver based on value written to this field. 3:0 eq1_sel r/w/u 0000 field selects between 0 to 9 db of eq for usb3.1 rx1 receiver. when eq_override = 1 ? b0, this field reflects the sampled state of eq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for usb3.1 rx1 receiver based on value written to this field. 8.6.7 usb3.1 control/status registers (address = 0x21) [reset = 00000000] figure 25. usb3.1 control/status registers (0x21) 7 6 5 4 3 2 1 0 reserved sseq_sel r r/w/u legend: r/w = read/write; r = read only; -n = value after reset table 17. usb3.1 control/status registers (0x21) bit field type reset description 7:4 reserved r 0000 reserved 3:0 sseq_sel r/w/u 0000 field selects between 0 to 11 db of eq for usb3.1 sstxp/n receiver. when eq_override = 1 ? b0, this field reflects the sampled state of sseq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for usb3.1 sstxp/n receiver based on value written to this field. 8.6.8 usb3.1 control/status registers (address = 0x22) [reset = 00000000] figure 26. usb3.1 control/status registers (0x22) 7 6 5 4 3 2 1 0 cm_active lfps_eq u2u3_lfps_d ebounce disable_u2u 3_rxdet dfp_rxdet_interval usb3_compliance_ctrl r/u r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 18. usb3.1 control/status registers (0x22) bit field type reset description 7 cm_active r/u 0 0 ? device not in usb 3.1 compliance mode. (default) 1 ? device in usb 3.1 compliance mode 6 lfps_eq r/w 0 controls whether settings of eq based on eq1_sel, eq2_sel and sseq_sel applies to received lfps signal. 0 ? eq set to zero when receiving lfps (default) 1 ? eq set to eq1_sel, eq2_sel, and sseq_sel when receiving lfps. 5 u2u3_lfps_debounce r/w 0 0 ? no debounce of lfps before u2/u3 exit. (default) 1 ? 200us debounce of lfps before u2/u3 exit. 4 disable_u2u3_rxdet r/w 0 0 ? rx.detect in u2/u3 enabled. (default) 1 ? rx.detect in u2/u3 disabled.
28 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated table 18. usb3.1 control/status registers (0x22) (continued) bit field type reset description 3:2 dfp_rxdet_interval r/w 00 this field controls the rx.detect interval for the downstream facing port (tx1p/n and tx2p/n). 00 ? 8 ms 01 ? 12 ms (default) 10 ? 48 ms 11 ? 96 ms 1:0 usb3_compliance_ctrl r/w 00 00 ? fsm determined compliance mode. (default) 01 ? compliance mode enabled in dfp direction (sstx - > tx1/tx2) 10 ? compliance mode enabled in ufp direction (rx1/rx2 - > ssrx) 11 ? compliance mode disabled.
29 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the tusb1046-dci is a linear redriver designed specifically to compensation for intersymbol interference (isi) jitter caused by signal attenuation through a passive medium like pcb traces and cables. because the tusb1046-dci has four independent displayport 1.4 inputs, one upstream facing usb 3.1 gen1/gen2 input, and two downstream facing usb 3.1 gen1/gen2 inputs, it can be optimized to correct isi on all those seven inputs through 16 different equalization choices. placing the tusb1046-dci between a usb3.1 host/displayport 1.4 gpu and a usb3.1 type-c receptacle can correct signal integrity issues resulting in a more robust system. 9.2 typical application figure 27. tusb1046-dci in a host application usb3.1 host TUSB1046A-DCI dp 1.4 gpu type-c receptacle a b c f d e g h dp0p dp0n dp1p dp1n dp2p dp2n dp3p dp3n tx1n tx1p tx2p tx2n rx1p rx1n rx2p rx2n pcb trace of length x ab pcb trace of length x ef pcb trace of length x gh pcb trace of length x cd ssrxp ssrxn sstxp sstxn copyright ? 2017, texas instruments incorporated
30 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated typical application (continued) 9.2.1 design requirements for this design example, use the parameters shown in table 19 . table 19. design parameters parameter value a to b pcb trace length, x ab 12 inches c to d pcb trace length, x cd 12 inches e to f pcb trace length, x ef 2 inches g to h pcb trace length, x gh 2 inches pcb trace width 4 mils ac-coupling capacitor (75 nf to 265 nf) 100 nf vcc supply (3 v to 3.6 v) 3.3 v i2c mode or gpio mode i2c mode. (i2c_en pin != "0") 1.8v or 3.3v i2c interface 3.3v i2c. pull-up the i2c_en pin to 3.3v with a 1k ohm resistor. 9.2.2 detailed design procedure a typical usage of the tusb1046-dci device is shown in figure 28 . the device can be controlled either through its gpio pins or through its i 2 c interface. in the example shown below, a type-c pd controller is used to configure the device through the i 2 c interface. when configured for i2c mode, pins 29 (rsvd1) and 32 (rsvd2) can be left unconnected. in i2c mode, the equalization settings for each receiver can be independently controlled through i2c registers. for this reason, all of the equalization pins (eq[1:0], sseq[1:0], and dpeq[1:0]) can be left unconnected. if these pins are left unconnected, the tusb1046-dci 7-bit i2c slave address will be 0x12 because both dpeq/a1 and sseq0/a0 will be at pin level "f". if a different i2c slave address is desired, dpeq/a1 and sseq0/a0 pins should be set to a level which produces the desired i2c slave address.
31 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated figure 28. application circuit a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a12 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b1 gnd gnd gnd gnd txp2 txn2 vbus vbus vbus vbus rxp2 rxn2 sbu1 dn1 dp1 cc1 txn1 txp1 rxp1 rxn1 sbu2 cc2 dp2 dn2 rx2p rx2n tx2p tx2n tx1n tx1p rx1n rx1p sbu1 sbu2 sstxp sstxn ssrxp ssrxn dp0p dp0n dp1p dp1n dp2p dp2n dp3p dp3n auxp auxn ssrxp ssrxn sstxp sstxn TUSB1046A-DCI auxp auxn dp_pwr (3.3v) 100k 100k 100 nf 100 nf 100nf 100nf 100nf 100nf 100nf 100nf 100nf 100nf 100nf 100nf 100nf 100nf 100nf 100nf 100nf 100nf dp_ml0p dp_ml0n dp_ml1p dp_ml1n dp_ml2p dp_ml2n dp_ml3p dp_ml3n usb 3.1 host dp1.4 gpu usb type-c receptacle flip/scl ctl0/sda ctl1/hpdin 2m 2m type-c pd controller i2c_en sseq0/a0 sseq1 dpeq0/a1 dpeq1 eq0 eq1 r 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v r v i2c vcc 100nf 10 p f 3.3v 100nf 100nf 100nf vcc vcc vcc tp copyright ? 2016, texas instruments incorporated dci_clk dci_dat ? ? to pch dci clock input to pch dci data input 22 o 22 o
32 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 9.2.3 application curve figure 29. insertion loss of fr4 pcb traces frequency (ghz) insertion loss (db) 0 2 4 6 8 10 12 14 16 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 d009 length=12in, width=6mil length=16in, width=6mil length=20in, width=6mil length=24in, width=6mil length=4in, width=4mil length=8in, width=10mil length=8in, width=6mil
33 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 9.3 system examples 9.3.1 usb 3.1 only the tusb1046-dci is in usb3.1 only when the ctl1 pin is low and ctl0 pin is high. figure 30. usb3.1 only ? no flip (ctl1 = l, ctl0 = h, flip = l) usb host gpu TUSB1046A-DCI type-c receptacle pd controller usb hub dp rx tusb1064 pd controller sstx ssrx sstx ssrx dp0 dp1 dp2 dp3 auxp auxn sbu1 sbu2 cc1 cc2 control hpd hpd control cc1 cc2 dp0 dp1 dp2 dp3 auxn auxp sbu1 sbu2 ctl flip 0 1 ctl1/0/flip=l/h/l 1 port usb ctl flip 0 1 tx1 tx2 rx1 rx2 tx2 tx1 rx2 rx1 hpdin hpdin d+/- type-c receptacle d+/- ctl1/0/flip=l/h/l copyright ? 2017, texas instruments incorporated
34 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated system examples (continued) figure 31. usb3.1 only ? with flip (ctl1 = l, ctl0 = h, flip = h) usb host gpu TUSB1046A-DCI type-c receptacle pd controller usb hub dp rx tusb1064 pd controller d+/- sstx ssrx sstx ssrx dp0 dp1 dp2 dp3 auxp auxn sbu1 sbu2 cc1 cc2 control hpd hpd control cc1 cc2 dp0 dp1 dp2 dp3 auxn auxp sbu2 ctl1/0/flip=l/h/h 1 port usb ctl flip 0 1 ctl flip 0 1 tx1 tx2 rx1 rx2 tx2 tx1 rx2 rx1 hpdin hpdin type-c receptacle d+/- sbu1 ctl1/0/flip=l/h/h copyright ? 2017, texas instruments incorporated
35 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated system examples (continued) 9.3.2 usb 3.1 and 2 lanes of displayport the tusb1046-dci operates in usb3.1 and 2 lanes of displayport mode when the ctl1 pin is high and ctl0 pin is high. figure 32. usb3.1 + 2 lane dp ? no flip (ctl1 = h, ctl0 = h, flip = l) usb host gpu TUSB1046A-DCI type-c receptacle pd controller usb hub dp rx tusb1064 pd controller sstx ssrx sstx ssrx dp0 dp1 dp2 dp3 auxp auxn sbu1 sbu2 cc1 cc2 control hpd hpd control cc1 cc2 dp0 dp1 dp2 dp3 auxn auxp sbu2 sbu1 ctl1/0/flip=h/h/l ctl1/0/flip=h/h/l 1 port usb & 2 lane dp ctl flip 0 1 ctl flip 0 1 tx1 tx2 rx1 rx2 tx2 tx1 rx2 rx1 hpdin hpdin d+/- d+/- type-c receptacle copyright ? 2016, texas instruments incorporated
36 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated system examples (continued) figure 33. usb 3.1 + 2 lane dp ? flip (ctl1 = h, ctl0 = h, flip = h) usb host gpu TUSB1046A-DCI pd controller usb hub dp rx tusb1064 type-c receptacle pd controller sstx ssrx sstx ssrx dp0 dp1 dp2 dp3 auxp auxn sbu1 sbu2 cc1 cc2 control hpd hpd control cc1 cc2 dp0 dp1 dp2 dp3 auxp auxn sbu2 sbu1 ctl1/0/flip=h/h/h ctl1/0/flip=h/h/h 1 port usb & 2 lane dp ctl flip 0 1 ctl flip 0 1 tx1 tx2 rx1 rx2 tx2 tx1 rx2 rx1 hpdin hpdin d+/- d+/- type-c receptacle copyright ? 2016, texas instruments incorporated
37 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated system examples (continued) 9.3.3 displayport only the tusb1046-dci operates in 4 lanes of displayport only mode when the ctl1 pin is high and ctl0 pin is low. figure 34. four lane dp ? no flip (ctl1 = h, ctl0 = l, flip = l) usb host gpu TUSB1046A-DCI type-c receptacle pd controller usb hub dp rx tusb1064 pd controller d+/- sstx ssrx sstx ssrx dp0 dp1 dp2 dp3 auxp auxn sbu1 sbu2 cc1 cc2 control hpd hpd control ctl1/0/flip=h/l/l ctl1/0/flip=h/l/l 4 lane dp ctl flip 0 1 ctl flip 0 1 tx1 tx2 rx1 rx2 tx2 tx1 rx2 rx1 hpdin hpdin d+/- type-c receptacle cc1 cc2 sbu1 sbu2 dp0 dp1 dp2 dp3 auxn auxp copyright ? 2017, texas instruments incorporated
38 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated system examples (continued) figure 35. four lane dp ? with flip (ctl1 = h, ctl0 = l, flip = h) 10 power supply recommendations the tusb1046-dci is designed to operate with a 3.3-v power supply. levels above those listed in the absolute maximum ratings table should not be used. if using a higher voltage system power supply, a voltage regulator can be used to step down to 3.3 v. decoupling capacitors should be used to reduce noise and improve power supply integrity. a 0.1- f capacitor should be used on each power pin. usb host gpu TUSB1046A-DCI type-c receptacle pd controller usb hub dp rx tusb1064 pd controller d+/- sstx ssrx sstx ssrx dp0 dp1 dp2 dp3 auxp auxn sbu1 sbu2 cc1 cc2 control hpd hpd control tx1 tx2 rx1 rx2 tx2 tx1 rx2 rx1 ctl1/0/flip=h/l/h ctl1/0/flip=h/l/h 4 lane dp ctl flip 0 1 ctl flip 0 1 hpdin hpdin d+/- type-c receptacle sbu1 sbu2 cc1 cc2 dp0 dp1 dp2 dp3 auxn auxp copyright ? 2017, texas instruments incorporated
39 TUSB1046A-DCI www.ti.com sllsf13 ? june 2017 product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 11 layout 11.1 layout guidelines 1. rxp/n and txp/n pairs should be routed with controlled 90- differential impedance ( 15%). 2. keep away from other high speed signals. 3. intra-pair routing should be kept to within 2 mils. 4. length matching should be near the location of mismatch. 5. each pair should be separated at least by 3 times the signal trace width. 6. the use of bends in differential traces should be kept to a minimum. when bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be 135 degrees. this will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on emi. 7. route all differential pairs on the same of layer. 8. the number of vias should be kept to a minimum. it is recommended to keep the vias count to 2 or less. 9. keep traces on layers adjacent to ground plane. 10. do not route differential pairs over any plane split. 11. adding test points will cause impedance discontinuity, and therefore, negatively impact signal performance. if test points are used, they should be placed in series and symmetrically. they must not be placed in a manner that causes a stub on the differential pair. 11.2 layout example figure 36. layout example to gpu to usb host to usb type-c receptacle ac coupling capacitors sstx ssrx rx2 tx2 tx1 rx1 dp0 dp1 dp2 dp3 aux sbu
40 TUSB1046A-DCI sllsf13 ? june 2017 www.ti.com product folder links: TUSB1046A-DCI submit documentation feedback copyright ? 2017, texas instruments incorporated 12 device and documentation support 12.1 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 20. related links parts product folder sample & buy technical documents tools & software support & community TUSB1046A-DCI click here click here click here click here click here tusb1046ai-dci click here click here click here click here click here 12.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks e2e is a trademark of texas instruments. vesa is a registered trademark of video electronics standards association corporation california. all other trademarks are the property of their respective owners. 12.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 15-nov-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TUSB1046A-DCIrnqr active wqfn rnq 40 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year 0 to 70 tusb46 TUSB1046A-DCIrnqt active wqfn rnq 40 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year 0 to 70 tusb46 tusb1046ai-dcirnqr active wqfn rnq 40 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tusb46 tusb1046ai-dcirnqt active wqfn rnq 40 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tusb46 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 15-nov-2017 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TUSB1046A-DCIrnqr wqfn rnq 40 3000 330.0 12.4 4.3 6.3 1.1 8.0 12.0 q2 TUSB1046A-DCIrnqt wqfn rnq 40 250 180.0 12.4 4.3 6.3 1.1 8.0 12.0 q2 tusb1046ai-dcirnqr wqfn rnq 40 3000 330.0 12.4 4.3 6.3 1.1 8.0 12.0 q2 tusb1046ai-dcirnqt wqfn rnq 40 250 180.0 12.4 4.3 6.3 1.1 8.0 12.0 q2 package materials information www.ti.com 2-nov-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TUSB1046A-DCIrnqr wqfn rnq 40 3000 367.0 367.0 35.0 TUSB1046A-DCIrnqt wqfn rnq 40 250 210.0 185.0 35.0 tusb1046ai-dcirnqr wqfn rnq 40 3000 367.0 367.0 35.0 tusb1046ai-dcirnqt wqfn rnq 40 250 210.0 185.0 35.0 package materials information www.ti.com 2-nov-2017 pack materials-page 2
www.ti.com package outline c 40x 0.25 0.15 4.70.1 40x 0.5 0.3 0.8 max (0.2) typ 0.05 0.00 36x 0.4 2x 2.8 2x 4.4 2.70.1 a 6.1 5.9 b 4.1 3.9 wqfn - 0.8 mm max height rnq0040a plastic quad flatpack - no lead 4222125/b 01/2016 pin 1 index area 0.08 seating plane 1 8 21 28 9 20 40 29 (optional) pin 1 id 0.1 c a b 0.05 exposed thermal pad notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. scale 2.500
www.ti.com example board layout 0.05 min all around 0.05 max all around 40x (0.2) 40x (0.6) ( ) typ via 0.2 36x (0.4) (3.8) (5.8) 4x (1.1) (4.7) (r ) typ 0.05 (2.7) 2x (2.1) 6x (0.75) wqfn - 0.8 mm max height rnq0040a plastic quad flatpack - no lead 4222125/b 01/2016 symm 1 8 9 20 21 28 29 40 symm land pattern example scale:15x notes: (continued) 4. this package is designed to be soldered to a thermal pad on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271). solder mask opening metal under solder mask solder mask defined metal solder mask opening solder mask details non solder mask defined (preferred)
www.ti.com example stencil design 40x (0.6) 40x (0.2) 36x (0.4) (5.8) (3.8) 6x (1.3) 6x (0.695) 4x (1.5) (r ) typ 0.05 6x (1.19) wqfn - 0.8 mm max height rnq0040a plastic quad flatpack - no lead 4222125/b 01/2016 notes: (continued) 5. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. symm metal typ solder paste example based on 0.1 mm thick stencil exposed pad 73% printed solder coverage by area scale:18x symm 1 8 9 20 21 28 29 40
important notice texas instruments incorporated (ti) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. ti ? s published terms of sale for semiconductor products ( http://www.ti.com/sc/docs/stdterms.htm ) apply to the sale of packaged integrated circuit products that ti has qualified and released to market. additional terms may apply to the use or sale of other types of ti products and services. reproduction of significant portions of ti information in ti data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such reproduced documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyers and others who are developing systems that incorporate ti products (collectively, ? designers ? ) understand and agree that designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that designers have full and exclusive responsibility to assure the safety of designers ' applications and compliance of their applications (and of all ti products used in or for designers ? applications) with all applicable regulations, laws and other applicable requirements. designer represents that, with respect to their applications, designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. designer agrees that prior to using or distributing any applications that include ti products, designer will thoroughly test such applications and the functionality of such ti products as used in such applications. ti ? s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, ? ti resources ? ) are intended to assist designers who are developing applications that incorporate ti products; by downloading, accessing or using ti resources in any way, designer (individually or, if designer is acting on behalf of a company, designer ? s company) agrees to use any particular ti resource solely for this purpose and subject to the terms of this notice. ti ? s provision of ti resources does not expand or otherwise alter ti ? s applicable published warranties or warranty disclaimers for ti products, and no additional obligations or liabilities arise from ti providing such ti resources. ti reserves the right to make corrections, enhancements, improvements and other changes to its ti resources. ti has not conducted any testing other than that specifically described in the published documentation for a particular ti resource. designer is authorized to use, copy and modify any individual ti resource only in connection with the development of applications that include the ti product(s) identified in such ti resource. no other license, express or implied, by estoppel or otherwise to any other ti intellectual property right, and no license to any technology or intellectual property right of ti or any third party is granted herein, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti products or services are used. information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. use of ti resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. ti resources are provided ? as is ? and with all faults. ti disclaims all other warranties or representations, express or implied, regarding resources or use thereof, including but not limited to accuracy or completeness, title, any epidemic failure warranty and any implied warranties of merchantability, fitness for a particular purpose, and non-infringement of any third party intellectual property rights. ti shall not be liable for and shall not defend or indemnify designer against any claim, including but not limited to any infringement claim that relates to or is based on any combination of products even if described in ti resources or otherwise. in no event shall ti be liable for any actual, direct, special, collateral, indirect, punitive, incidental, consequential or exemplary damages in connection with or arising out of ti resources or use thereof, and regardless of whether ti has been advised of the possibility of such damages. unless ti has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., iso/ts 16949 and iso 26262), ti is not responsible for any failure to meet such industry standard requirements. where ti specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. using products in an application does not by itself establish any safety features in the application. designers must ensure compliance with safety-related requirements and standards applicable to their applications. designer may not use any ti products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). such equipment includes, without limitation, all medical devices identified by the u.s. food and drug administration as class iii devices and equivalent classifications outside the u.s. ti may expressly designate certain products as completing a particular qualification (e.g., q100, military grade, or enhanced product). designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at designers ? own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2017, texas instruments incorporated

▲Up To Search▲

Price & Availability of TUSB1046A-DCI

	To Download TUSB1046A-DCI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .